1. Technical Field
The present invention relates to data processing systems, and more particularly to a method and apparatus for changing bus speed fractions on a bus that operates at a fraction of a microprocessor core frequency.
2. Background Art
The above reference U.S. Pat. No. 5,471,587 of Roshan Fernando et al. provides a bus timing apparatus that operates in fractional speed modes without inserting extra clock cycles or by adding wait states. This bus liming apparatus will find use in future IBM Personal Computers that are marketed to various market segments at price/performance levels that are related to various clock speeds at which the microprocessor operates, at proportionally increasing prices. The clock speed determines the kinds of peripheral devices, such as printers and monitors, and memory devices that can be used with the base machine. The above referenced U.S. Pat. No. 5,471,587 of Roshan Fernando et al. discloses a bus timing apparatus that couples internal higher speed buses with slower external busses operating at a fraction of the internal bus frequency. This bus timing apparatus enables a slower I/O device or memory module to match the higher speeds of the microprocessors. In order for such a bus timing apparatus to be commercially viable, it is necessary that a user be able to change bus speed or stop and start the clock without having to reset the computer.
It is therefore desirable to provide a method and apparatus for changing bus speed fractions and slopping and restarting a clock on a bus that operates at a fraction of the microprocessor core frequency.